The present invention relates to methods of sputtering and, more particularly, to methods of respurttering layers of electrically insulative materials used in integrated semiconductor circuits. In the construction of thin film integrated semiconductor circuits wherein the passivating or insulating layer is deposited over a non-planar integrated circuit substrate, e.g., a substrate having etched recesses or one having a raised conductive line pattern, the insulative layer will follow the contours of the underlying non-planar substrate, i.e., the insulative layer will have raised portions or elevations corresponding to the elevations in the non-planar substrate.
As set forth in U.S. Pat. No. 3,804,738, the art has recognized the advantages of removing all elevations from a deposited insulative layer by resputtering to planarize the surface of the layer. Such planarization of insulative layers was considered to be particularly desirable in structures having several levels of metallurgy separated by several layers of insulative material. In such multi-layered structures, cumulative effects of several levels of raised metallization of the final insulative layer would be very pronounced and undesirable. Consequently, the advantage of completely planarizing each of several insulative layers to avoid the overall cumulative effect is apparent. Such complete planarization by resputtering is very effective. However, it is very time-consuming. For example, it takes up to about twenty-four hours of RF resputtering to completely planarize a conventional silicon dioxide layer deposited over a metallization pattern having raised lines in the order of from 300 to 1500 micro-inches in width, a conventional width for present-day integrated circuit structures.
The phenomenon of resputtering, in general, is known in the art and involves the re-emission of deposited insulative material, such as SiO.sub.2, during the sputter deposition thereof through the effects of attendant ion bombardment of the deposited insulative layer. This resputtering approach was first disclosed in the publication. "Thin Films Deposited by Bias Sputtering," L. I. Maissel et al., Journal of Applied Phsyics, January 1965, p. 237, as a modified DC sputtering technique known as Biased Sputtering. The application of the principles of resputtering to RF sputtering is disclosed in an article, "Re-Emission Coefficients of Silicon and Silcion Dioxide Films Deposited Through RF and DC Sputtering," R. E. Jones et al., Journal of Applied Physics, Nov. 1967, p. 4656. In effect, resputtering is the positive ion bombardment of an insulative film during its deposition. The prior art has recognized that resputtering improves the quality of sputter deposited film; U.S. Pat. No. 3,661,761, discloses the use of RF sputtering to improve film quality and uniformity.
While resputtering has been used to some extent in the commerical fabrication of integrated circuits for the purpose of improving the quality of sputter deposited film, the use of resputtering for complete planarization has been quite limited because of the great amount of time necessary to achieve complete planarization of an insulative layer deposited over raised metallized line patterns of conventional width.
In addition, the use of deposited layers of insulative material in forming lateral dielectric isolation in integrated circuits has been very limited because of the absence of an effective technique for planarizing a layer of deposited insulative material so that the surface of the insulative layer over unrecessed portions of the substrate is substantially coplanar with the surface of insulative material deposited in the recesses in the substrate to provide the dielectric isolation.
Such dielectrically isolated integrated circuits are characterized by patterns of moats or trenches extending from the surface of a semiconductor substrate to isolate respectively a plurality of pockets on the semiconductor material. Where the dielectric or insulative layers are deposited over such mesa-like structures, the result is a pattern of steps or elevations in the insulated layer corresponding to the pattern of mesas in the substrate. Depending on the techniques utilized to fill the trenches or moats with dielectric material, these steps may often be quite steep which, as previously mentioned, could result in discontinuities in the metallization placed on the insulative layer.
In order to avoid such variation in the insulative layer, one approach in the art has been to oxidize the silicon substrate surrounding the trench or moat by heating to form thermal oxide which fills in the trench providing the lateral insulation and a relatively planar surface upon which surface insulative layers can thereafter be applied. This process is described in detail in an article entitled, "Local Oxidation of Silicon and Its Applications in Semiconductor Device Technology," J. A. Appels et al, Phillips Research Reports 25, p. 118, 1970. While this approach may be used in methods where it is possible to oxidize the substrate in situ to fill in the trenches, the art has yet to develop a practical approach wherein planarization may be achieved in a method wherein the trenches are filled with the dielectric or insulative material by deposition techniques such as vapor deposition or RF sputter deposition. The problems involved in the planarization of such deposited insulative layers are essentially the same as those previously described with respect to planarization of insulative layers over a metallization pattern except that the steps or elevations often tend to be even higher, thereby making the problem even more difficult.
As an alternative to resputtering, the prior art has also considered an approach involving masking the depressed areas or valleys with an etch-resistant material such as photoresist through conventional photolithographic techniques, and then etching to remove the uncovered elevations or steps. This approach often runs into problems with photoresist mask alignment. In high density large-scale integrated circuits, the dimensions are so minute that difficulties may be encountered in obtaining the exact registration required to completely mask the depressed areas or valleys with photoresist. Any misalignment which leaves a portion of a depressed area exposed could result in an etch through the insulative layer in said depressed area simultaneously with the planarization of the elevated area. This will result in an undesirable short circuit path through the insulative layer in the depressed area.